// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_epf_cfgspace_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_H__
#define __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_H__

/* HIPCIEC_EPF_CFGSPACE Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE                       (0x85000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_EPF_CFGSPACE Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_ID_REG                       (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x0)   /* This register specify the register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_CMDSTS_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x4)   /* This register specify the register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_CLSREV_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8)   /* This register specify the register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_MISC_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xC)   /* This register specify the register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR0_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x10)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR1_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x14)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR2_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x18)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR3_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x1C)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR4_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x20)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR5_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x24)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_CBUS_PTR_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x28)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_SUBSYS_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_EXPROM_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x30)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_CAPPTR_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x34)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCI_RSVD_REG                        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x38)  /* reserved */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIHDR_INT_REG                      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C)  /* This register specify the base address register of config space. */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PCIE_CAP_HEADER_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x40)  /* This is the pcie capability header register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPBILITY_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x44)  /* This register describe the device capability */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL_STATUS_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x48)  /* device control status register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CAPBILITY_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x4C)  /* Link capability register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x50)  /* Link control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SLOT_CAPABILITY_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x54)  /* Slot capability register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_STATUS_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x58)  /* Slot control and status register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ROOT_CTRL_STATUS_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x5C)  /* Root control status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ROOT_STATUS_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x60)  /* Root status register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPABILITY2_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x64)  /* device capability 2 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL2_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x68)  /* Device control register 2 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CAPABILITY2_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x6C)  /* Link capability 2 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS2_REG               (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x70)  /* Link control and status 2 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SLOT_CAP_2_REG                      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x74)  /* Slot Capabilities 2 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_2_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x78)  /* Slot Control 2 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_CAP_HEADER_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x80)  /* MSI control and ID regisiter */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_LADDR_REG                       (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x84)  /* MSI low address */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_HADDR_REG                       (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x88)  /* MSI uppr address */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_DATA_REG                        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8C)  /* MSI data register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_MASK_REG                        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x90)  /* MSI mask register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSI_PENDING_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x94)  /* MSI pending register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSIX_CAP_HEADER_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xA0)  /* MSIX control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_CTRL_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xA4)  /* MSIX table control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_MSIX_PBA_CTRL_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xA8)  /* MSIX pending bit array control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PME_CAP_ID_REG                      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xB0)  /* PME capability header and PME control */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_PME_STATUS_REG                      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0xB4)  /* Power management status register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_AER_CAP_HEADER_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_STATUS_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x104) /* uncorrectable error status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_MASK_REG                   (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_SEVERITY_REG               (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_COR_ERR_STATUS_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x110) /* Correctable error status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_COR_ERR_MASK_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x114) /* correctable error mask */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ADVACD_CAP_CTRL_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_FIRST_HEADER_LOG_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x11C) /* First DW header log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SECOND_HEADER_LOG_REG               (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x120) /* Second DW header log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_THIRD_HEADER_LOG_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x124) /* Third DW header log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_FOUR_HEADER_LOG_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x128) /* Forth DW header log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_COMMAND_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x12C) /* Root error report command */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_STATUS_REG               (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x130) /* Roor Error status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ERR_SOURCE_IDEN_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x134) /* Erorr soure identification register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_FIRST_PREFIX_LOG_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x138) /* First DW prefix log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SECOND_PREFIX_LOG_REG               (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x13C) /* Second DW prefix log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_THIRD_PREFIX_LOG_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x140) /* Third DW prefix log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_FOUR_PREFIX_LOG_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x144) /* Forth DW prefix log */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ARI_CAP_HEADER_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x150) /* ARI capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ARI_CTRL_REG                        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x154) /* ARI control and capability */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_HEADER_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x200) /* SRROIOV capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_REG                       (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x204) /* SRROIOV capability */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SRIOV_CTRL_REG                      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x208) /* SRROIOV control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_INIT_VF_NUMBER_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x20C) /* Initial VF and Totla VF */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_FUNC_DEP_VF_NUM_REG                 (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x210) /* Function dependency link and VF NUMBER */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_RID_SETTING_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x214) /* First offset and Stride register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_DEVICE_ID_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x218) /* VF device ID */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_PAGE_SIZE_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x21C) /* supported Page Size */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SYSTEM_PAGE_SIZE_REG                (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x220) /* System page size */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR0_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x224) /* Virtual function  Base address 0  register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR1_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x228) /* Virtual function  Base address 1 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR2_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x22C) /* Virtual function  Base address 2 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR3_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x230) /* Virtual function  Base address 3 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR4_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x234) /* Virtual function  Base address 4 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_BAR5_REG                         (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x238) /* Virtual function  Base address 5 register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_ARRAY_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x23C) /* VF Migration state array offset */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ATS_CAP_HEADER_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x260) /* Address translation service capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ATS_CAP_CTRL_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x264) /* ATS capability and control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_TPH_EXTEND_CAP_REG                  (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CAP_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A4) /* tph request capability register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CTRL_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A8) /* tph requester control register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SECONDARY_PCIE_EXT_CAP_HED_REG      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x310) /* Secondary PCI Express Extended Capability Header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER_REG          (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x314) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LANE_ERROR_STATUS_REG_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x318) /* Lane Error Status Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER01_REG        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x31C) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER23_REG        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x320) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER45_REG        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x324) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER67_REG        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x328) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER89_REG        (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x32C) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1011_REG      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x330) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1213_REG      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x334) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1415_REG      (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x338) /* Link Control 3 Register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DEVICE_SERIAL_NUMBER_CAP_HEADER_REG (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E0) /* device serial number extended capability header */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SERIAL_LNUM_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E4) /* serial low number register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_SERIAL_HNUM_REG                     (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E8) /* serial high number register */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X00_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x630) /* ACS capability register 00 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X04_REG                    (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x634) /* ACS capability register 04 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG00_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x700) /* DL feature capability register 00 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG04_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x704) /* DL feature capability register 04 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG08_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x708) /* DL feature capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG00_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x70C) /* RX Margin capability register 00 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG04_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x710) /* RX Margin capability register 04 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_0_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x714) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_1_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x718) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_2_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x71C) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_3_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x720) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_4_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x724) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_5_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x728) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_6_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x72C) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_7_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x730) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_8_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x734) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_9_REG            (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x738) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_10_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x73C) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_11_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x740) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_12_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x744) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_13_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x748) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_14_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x74C) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_15_REG           (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x750) /* RX Margin capability register 08 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG00_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x880) /* Gen4 phy txpreset capability register 00 */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG04_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x884) /* reserved */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG08_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x888) /* reserved */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG0C_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x88C) /* gen4 equalization req and status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG10_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x890) /* local link data parity status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG14_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x894) /* retimer link data parity status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG18_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x898) /* second retimer link data parity status */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG1C_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x89C) /* reserved */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG20_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A0) /* Gen4 tx preset */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG24_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A4) /* Gen4 tx preset */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG28_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A8) /* Gen4 tx preset */
#define HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG2C_REG              (HiPCIECTRL40V200_HIPCIEC_EPF_CFGSPACE_BASE + 0x8AC) /* Gen4 tx preset */

#endif // __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_H__
